The present disclosure relates to a semiconductor storage device and its configurations for reducing current in standby mode.
Reducing current in standby mode of a Static Random Access Memory (SRAM) has so far been pursued. Circuits are proposed which are configured to reduce current by controlling the potential of source lines and lowering voltage that is applied to memory cells in standby mode in which the memory cells only retains data, but reading and writing data from/to them are not performed, apart from normal mode in which reading and writing data from/to the memory cells are performed.
In this respect, according to Japanese Published Unexamined Patent Application No. 2004-206745, a transistor serving as a power supply switch which is coupled to source lines of memory cells and a diode-coupled transistor are separately provided. The transistor serving as the power supply switch is controlled to be conducting in normal mode and non-conducting in standby mode, when the potential of source lines of memory cells is controlled by the diode-coupled transistor.
In a configuration according to Japanese Published Unexamined Patent Application No. 2007-150761, a single diode-coupled transistor is only provided and there is no transistor serving as a power supply switch which is coupled to source lines of memory cells. This transistor is conducting in normal mode to bring down the potential of source lines. In standby mode, the transistor will be diode-coupled with its gate set equal to the source potential of memory cells and controls the potential of source lines of memory cells.